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Espressif Systems /ESP32-S2 /SENS /SAR_COCPU_INT_CLR

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Interpret as SAR_COCPU_INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (COCPU_TOUCH_DONE_INT_CLR)COCPU_TOUCH_DONE_INT_CLR 0 (COCPU_TOUCH_INACTIVE_INT_CLR)COCPU_TOUCH_INACTIVE_INT_CLR 0 (COCPU_TOUCH_ACTIVE_INT_CLR)COCPU_TOUCH_ACTIVE_INT_CLR 0 (COCPU_SARADC1_INT_CLR)COCPU_SARADC1_INT_CLR 0 (COCPU_SARADC2_INT_CLR)COCPU_SARADC2_INT_CLR 0 (COCPU_TSENS_INT_CLR)COCPU_TSENS_INT_CLR 0 (COCPU_START_INT_CLR)COCPU_START_INT_CLR 0 (COCPU_SW_INT_CLR)COCPU_SW_INT_CLR 0 (COCPU_SWD_INT_CLR)COCPU_SWD_INT_CLR

Description

Interrupt clear bit of ULP-RISCV

Fields

COCPU_TOUCH_DONE_INT_CLR

TOUCH_DONE_INT interrupt clear bit
COCPU_TOUCH_INACTIVE_INT_CLR

TOUCH_INACTIVE_INT interrupt clear bit
COCPU_TOUCH_ACTIVE_INT_CLR

TOUCH_ACTIVE_INT interrupt clear bit
COCPU_SARADC1_INT_CLR

SARADC1_DONE_INT interrupt clear bit
COCPU_SARADC2_INT_CLR

SARADC2_DONE_INT interrupt clear bit
COCPU_TSENS_INT_CLR

TSENS_DONE_INT interrupt clear bit
COCPU_START_INT_CLR

RISCV_START_INT interrupt clear bit
COCPU_SW_INT_CLR

SW_INT interrupt clear bit
COCPU_SWD_INT_CLR

SWD_INT interrupt clear bit

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd